Accelerator IP Design Engineer (ASIC, RTL)

About the role

Edgecortix is looking for a Hardware Design Engineer to develop RTL and ASIC modules for its AI inference accelerator IP. You will work on cutting‑edge digital chip designs that power real‑time AI on edge devices.

Key responsibilities

• Design RTL and perform module‑level verification for the accelerator IP.
• Participate in synthesis, static timing analysis, and power estimation.
• Implement micro‑architectural optimizations to meet area, power, and routability targets.
• Collaborate with architects and compiler engineers on new functionality and specifications.
• Integrate third‑party IPs in SoC designs and conduct system‑level verification using SystemVerilog and UVM.

Required profile

• Ability to write clean, readable, synthesizable RTL.
• Familiarity with AXI, Avalon or similar bus protocols.

Required skills

• RTL design and verification (SystemVerilog, UVM).
• Logic synthesis tools (Cadence, Synopsys).
• Timing constraints and power intent definition.
• Power analysis tools (Joules, PowerPro).
• Physical design awareness.
• Low‑power RTL techniques and fixed‑point arithmetic.
• High‑speed interfaces (DDR, PCI‑E, MIPI CSI) – a plus.
• Scripting/automation (TCL, Python, Make).
• Programming in C++ or Java.

What we offer

• Highly competitive salary and stock options.
• Flexible work time with the ability to work fully remotely.
• Visa and relocation support for non‑remote candidates.