Design Verification Engineer – AI Hardware Accelerator

About the role

Edgecortix is seeking an experienced Design Verification Engineer to join its Artificial Intelligence Hardware Accelerator team. You will work closely with design and architecture groups to build verification environments for next‑generation AI SoCs, contributing to cutting‑edge hardware‑software co‑design.

Key responsibilities

• Collaborate with the design architecture team on IP, performance and SoC verification.
• Develop verification infrastructure, including VIPs, memory models and monitors.
• Write configurable testbenches in SystemVerilog/UVM and automate testbench execution.
• Create and maintain SystemVerilog assertions.
• Define functional coverage and perform functional and code coverage analysis.
• Conduct ASIC power estimation and power‑aware verification.
• Automate tool flows and generate result reports.

Required profile

• 6‑7 years of functional verification experience using SystemVerilog/UVM.
• Strong knowledge of verification techniques such as assertions, metric‑driven and coverage‑driven methods.
• Proven ability to build verification infrastructure from scratch.
• Experience with high‑speed bus protocols (e.g., AXI4).
• Background in gate‑level simulations and delay modeling.
• Skilled in constraint‑random verification and functional/code coverage creation.
• Expertise in writing and debugging SystemVerilog assertions.
• Solid RTL debugging capabilities.

Required skills

• SystemVerilog and UVM
• Verification IPs (VIPs)
• AXI4, PCI‑E, DDR protocols
• Gate‑level simulation and delay modeling
• Constraint‑random verification
• Functional and code coverage analysis
• RTL and testbench debugging
• Continuous Integration tools (Jenkins, GitLab CI, Circle CI)
• Cadence tools (Genus, Joules, Conformal)
• Standard cell libraries
• Perl and Python scripting

What we offer

• Highly competitive salary and stock options.
• Flexible work time with the possibility to work fully remotely.
• Visa assistance and relocation support for non‑remote candidates.